In advanced digital systems the propagation delay plays a vital role to optimize the performance of an individual processing element. To achieve parallelism in advanced processors, pipeline technique is the best method proposed by many manufacturers. The Propagation delay is one of the important factor need to consider in pipeline design. In the present paper the advantages and flaws of various pipelines are discussed. And a new clock scheme is proposed, to minimize the propagation delay in pipeline stages. In the present paper the performance evaluation is done in terms of various parameters like timing delay, throughout etc.

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