In this paper, a greedy algorithm using Simulated Annealing is proposed for the FPGA placement problem. The algorithm is implemented with a simulation program. It finds optimal answer in some cases and near optimal in other cases. However, the aim of this paper is not to devise an algorithm to compete with VPR results. The algorithm itself is only a suggestion to consider more greedy parameters along with approximation algorithms for such an NP-Complete Problem. The other concern of the paper is to demonstrate the simulation program and its different parts, some implementation issues and fascinating results of both developing and running the program. The simulation program is user friendly and flexible. It gains the ability of controlling the algorithm\'s parameters as input values and allows the results to be used for initial setting of further runs in a friendly manner. It visualizes the SA FPGA placement in a suitable manner to be used for educational issues.

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