A multi-threshold design can be achieved by employing CNTs with different diameters, as the threshold voltage of the CNTFET depends on the diameter of the CNT. In this paper, this feature is exploited to design ternary logic circuits for achieving improved performance. We presented new design for Carbon Nanotube Field Effect Transistor (CNTFET) based ternary combinational circuits such as half adder, full adder, half subtractor, full subtractor and comparator using negation of literals technique. Extensive simulation results using Synopsis HSPICE simulator demonstrate that using new technique 5 to 29 times improvement in power delay product can be achieved with reduced gate count comparing to the existing ternary-binary combinational gate design.

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